Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
Aspects of semiconductor fabrication have focused on providing highly integrated semiconductor devices. Such semiconductor devices may include metal wirings on a circuit having a micro line width whereby the distance between the lines is also very small. In order to reduce the size of the devices, a multi-layered wiring structure may be required. The multi-layered wirings may require dielectric layers for providing electrical insulation between the components. In some applications, dielectric layers for providing electrical isolation between components, such as metal wirings, may be formed by depositing tetraethyl orthosilicate (Si(OC2H5)4) (hereinafter TEOS) using plasma enhanced chemical vapor deposition methods. In some other embodiments, the dielectric layers may be a low k dielectric material.
In the process of connecting and interconnecting electrical circuit elements with patterned conductor layers which are separated by the dielectric layers, for example, it is common in the art of integrated circuit fabrication to form vias and other apertures through the dielectric layers such that conductive connections may be made between the patterned conductor layers and the electrical circuit elements which are separated by the dielectric layers. Vias and other apertures within and/or through dielectric layers, such as a PMD layer, of integrated circuits are commonly formed through photolithographic methods followed by etch methods.
For example, in some typical sub 20 nanometer semiconductor applications a silicon carbonitride (SiCN) dielectric mask layer is formed on a substrate (e.g., silicon wafer) over a PMD dielectric layer and/or a metal layer. In some such embodiments the SiCN dielectric mask layer is a nitrogen-doped silicon carbide mask layer. In some embodiments the dielectric layer is a TEOS or a low k dielectric material. In some embodiments the metal layer is a layer of W, Al and/or Cu.
The SiCN dielectric mask layer not only serves as a mask layer, but as a chemical-mechanical planarization (CMP) stopping layer and a metal layer cap (e.g., copper contacts to source/drain, gate, etc lined with tungsten). Degradation of the dielectric mask layer during fabrication would thereby result in interlayer leakage, which in turn leads to performance loss in the resulting integrated circuit.
A photoresist layer is typically deposited on the SiCN dielectric mask layer, which is deposited on a dielectric layer and/or a metal layer. The photoresist layer is utilized by etching processes to form an opening or through-silicon via (TSV) hole or trench for the formation of a TSV through the layers. After the opening or TSV hole is formed via etching (and after potentially ion implantation), the photoresist is removed from the SiCN dielectric mask layer by ashing, and then the SiCN dielectric mask layer is wet cleaned by diluted HF solution.
The removal of the photoresist after etching is one of the most important and frequently performed steps in front-end semiconductor manufacturing. Depending on the complexity of the devices concerned, many lithography cycles are required and each cycle requires a photoresist removal process, potentially from SiCN dielectric mask layer that also serves as a chemical-mechanical planarization (CMP) stopping layer and a contact capping layer (as described above). Removal of photoresist can be achieved several ways. Positive photoresist can be removed using acetone followed by water rinse. Other less flammable and more aggressive solvents can be used on both negative and positive resists. A dry technique of photoresist stripping, “ashing,” involves removal by volatilization of the photoresist (e.g., organic materials) from the SiCN dielectric mask layer using strongly oxidizing ambient. The preferred type of the ashing stripping approach is oxygen plasma ashing because it uses only small amounts of oxygen and does not include the chemical waste problems associated with other removal methods. In essence, oxygen plasma ashing involves combining oxygen with the photoresist via oxygen plasma to form ash which is removed by a vacuum pump. In this way, the process of oxygen plasma ashing is usually restricted to the removal of the organic matter of the photoresist by oxygen plasma. The by-products of oxygen plasma ashing are typically carbon oxides and water vapor, which are volatile and typically pumped away by the vacuum system.
Oxygen plasma ashing of photoresist on an SiCN dielectric mask layer can lead to degradation of the SiCN dielectric mask layer. For example, the oxygen of the oxygen plasma of the ashing process can deplete at least a substantial portion the carbon of the SiCN dielectric mask layer (e.g., a SiCNH layer) and thereby leave the SiCN dielectric mask layer substantially weak. In some such scenarios, the SiCN dielectric mask layer may contain about 10 to about 30 wt % carbon, and substantially all of the carbon may be depleted from at least some portions of the SiCN dielectric mask layer. The weak, carbon-depleted SiCN dielectric mask layer is then removed or stripped from the dielectric layer and/or a metal layers during the ashing, cleaning and/or other subsequent process steps. For example, at least about 40% of the weak, carbon-depleted SiCN dielectric mask layer can be removed from the dielectric layer and/or metal layers during the ashing, cleaning and/or other subsequent process steps. In some embodiments, at least some portions of the weak, carbon-depleted SiCN dielectric mask layer is completely removed from the dielectric layer and/or metal layers during the ashing, cleaning and/or other subsequent process steps. As the SiCN dielectric mask layer serves as a mask layer, a chemical-mechanical planarization (CMP) stopping layer, and a metal layer capping layer (as described above), the at least partial removal of the SiCN dielectric mask layer can lead to interlayer leakage and thereby performance loss in the resulting integrated circuit.
Thus, the fabrication of a semiconductor device with can be problematic with existing fabrication techniques and improved device fabrication techniques are needed for forming devices with a substantially intact or at least substantially effective dielectric mask layer applied over a dielectric layer and/or a metal layer.